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Bit
Name
Reset
Access
Description
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2:0
MODE
0x1
RW
Read Mode
After reset, the core clock is 14 MHz from the HFRCO and the MODE field of MSC_READCTRL register is set to WS1. The reset
value is WS1 because the HFRCO may produce a frequency above 16 MHz before it is calibrated. WS1 or WS1SCBTP mode is
required for a frequency above 16 MHz. If software wants to set a core clock frequency above 16 MHz, this register must be set to
WS1 or WS1SCBTP before the core clock is switched to the higher frequency. When changing to a lower frequency, this register
can be set to WS0 or WS0SCBTP after the frequency transition has been completed. If the HFRCO is used as clock source, wait
until the oscillator is stable on the new frequency to avoid unpredictable behavior.
Value
0
1
2
3
Mode
WS0
WS1
WS0SCBTP
WS1SCBTP
Description
Zero wait-states inserted in fetch or read transfers
One wait-state inserted for each fetch or read transfer. This mode is required for a core
frequency above 16 MHz.
Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch
(SCBTP) function enabled. SCBTP saves energy by delaying Cortex-M3 conditional
branch target prefetches until the conditional branch instruction is in the execute stage.
When the instruction reaches this stage, the evaluation of the branch condition is
completed and the core does not perform a speculative prefetch of both the branch
target address and the next sequential address. With the SCBTP function enabled,
one instruction fetch is saved for each branch not taken, with a negligible performance
penalty.
One wait-state access with SCBTP enabled.
7.5.3 MSC_WRITECTRL - Write Control Register
Offset
0x008
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
IRQERASEABORT
0
RW
Abort Page Erase on Interrupt
When this bit is set to 1, any Cortex-M3 interrupt aborts any current page erase operation. If the CPU reads the interrupt vectors from
Flash in this case, the CPU can enter an unpredictable state. This can be avoided by moving the interrupt vectors to RAM.
0
WREN
0
RW
Enable Write/Erase Controller
When this bit is set, the MSC write and erase functionality is enabled
7.5.4 MSC_WRITECMD - Write Command Register
Offset
0x00C
Reset
Access
Name
Bit Position
2011-04-12 - d0001_Rev1.10
33
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